Amiga Format CD 38

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Text File | 1999-02-10 | 36KB | 933 lines

NEW AGA-ECS REGISTERS: (thanx to DDT/HBT for ECS help) ;CUSTOM = $DFF000 vposr EQU $004 ; Read vertical most significant bits (and frame flop) Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Use LOF I6 I5 I4 I3 I2 I1 I0 LOL -- -- -- -- v10 v9 V8 LOF=Long frame(auto toggle control bit in BPLCON0) I0-I6 Chip identitication: 8361 (Regular) or 8370 (Fat) (Agnus-ntsc)=10 8367 (Pal) or 8371 (Fat-Pal) (Agnus-pal)=00 8372 (Fat-hr) (agnushr),thru rev4 = 20 Pal,30 NTSC 8372 (Fat-hr) (agnushr),rev 5 = 22 Pal, 31 NTSC 8374 (Alice) thru rev 2 = 22 Pal, 32 NTSC 8374 (Alice) rev 3 thru rev 4 = 23 Pal, 33 NTSC LOL = Long line bit. When low, it indicates short raster line. v9,10 -- hires chips only (20,30 identifiers) * cdang EQU $02e ; Copper control register This is a 1-bit register that when set true, allows the copper to access the blitter hardware. This bit is cleared by power-on reset, so that the copper cannot access the blitter hardware. 01 CDANG (STD) Copper danger mode. Allows Copper access to blitter if set ($DFF03E to $DFF07E). (ECS) If clear copper can only access addresses ($DFF03E to $DFF07E). If set copper can access all chip registers. * STREQU EQU $038 ;Strobe for horiz sync with VB (vert blank) and EQU STRVBL EQU $038 ;Strobe for horiz sync with VB STRHOR EQU $03C ;Strobe for horiz sync STRLONG EQU $03E ;Strobe for identification of long horiz line (228cc) One of the first 3 strobe addresses above, it is placed on the RGA bus during the first refresh time slot of every other line, to identify lines with long counts (228- NTSC, HTOTAL+2- VARBEAMEN=1 hires chips only).There are 4 refresh time slots and any not used for strobes will leave a null (1FE) address on the RGA bus. * pad2d EQU $05A ; note: byte access only ; function unknown * bltcon0l EQU $05B ; note: byte access only - write only ; Blitter control 0, lower 8 bits (minterms) The BLTCON0L register writes the low bits of BLTCON0, thereby expediting the set up of some blits and generally speeding up the software, since the upper bits are often the same. * bltcon1 EQU $042 ; Blitter control register 1 Bit 7 (DOFF) of the BLTCON1 register, when set, disables the output of the Blitter hardware on channel D. This allows inputs to channels A, B and C and certain address modification if necessary, without the Blitter outputting over channel D. * bltsizv EQU $05C ; Blitter Size Vertical 0 H14 H13 H12 H11 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 H0 H=Height (32768 lines Max) * bltsizh EQU $05E ; Blitter Size Horizontal 0 0 0 0 0 W10 W9 W8 W7 W6 W5 W4 W3 W2 W1 W0 W=Width in words (2048 words = 32768 pixels Max) Writing this register starts the Blitter With these two registers, blits up to 32K by 32K are now possible - much larger than the original chip set could accept. The original commands are retained for compatibility. BLTSIZV should be written first, followed by BLTSIZH, which starts the blitter. * pad34 EQU $068-$06a-$06c-$06e ;UNUSED * pad3b EQU $076 ;UNUSED * BPLHDAT EQU $07A ;Ext logic UHRES bit plane identifier * SPRHDAT EQU $078 ;Ext logic UltraHiRes sprite pointer and data identif. This identifies the cycle when this pointer address is on the bus accessing the memory. * deniseid EQU $07C ; (or Lisaid) Denise chip ID (to check the chipset) Lower 8 bits: - Random value if standard Denise is present - $FC if ECS Denise is present - $F8 if AGA chipset is present The original Denise (8362) does not have this register, so whatever value is left over on the bus from the last cycle will be there. ECS Denise (8373) returns hex (fc) in the lower 8 bits.Lisa returns hex (f8). The upper 8 bits of this register are loaded from the serial mouse bus, and are reserved for future hardware implentation. The 8 low-order bits are encoded as follows: (from C-18 AGA doc) BIT# Description ---- -------------------------------------------------- 7-4 Lisa/Denise/ECS Denise Revision level(decrement to bump revision level, hex F represents 0th rev. level). 3 Maintain as a 1 for future generation 2 When low indicates AA feature set (LISA) 1 When low indicates ECS feature set (LISA or ECS DENISE) 0 Maintain as a 1 for future generation * bplcon0 EQU $100 ; 15 = HIRES ; 14 = BPU2 \ ; 13 = BPU1 |select num of bitplanes, from 0 thru 7 ; 12 = BPU0 / ; 11 = HAM - old HAM, and HAM8 AGA (if bit 4 is set) ; 10 = DBLPF - double playfield ; 9 = COLOR - Composite video (Genlock) ; 8 = GAUD - Composite audio ; 7 = UHRES - 1024*1024 (set also bit 9 in DMACON) ; 6 = superhires 1280x 35ns ; 5 = BPLHWRM - screen black and white, no copcolors ;BYPASS = 0 ; 4 = 8 planes (then bits 12-14 must be 0) ; 3 = LPEN - Light pen ; 2 = LACE - Interlace mode ; 1 = ERSY - External resync ; 0 = ECSENA Enable bplcon3 register (ECS-AGA) bit 7 of $dff100 is the UHRES bit (ultra hires is think)...i don't know how this works exactly but my suspicions is that it is 1024*1024 and i only 1 bitplane deep... the bitplane pointer for UHRES is $dff1ec and $dff1ee!!!! so its a new bitplanepointer!!!! it only works in vram (what the hell is that anyway??) you have also a vram spritepointer extra... (also uhres!!)..(also needs bits in DMACON). Disables hard stops for vert, horiz display windows BYPASS = Bitplanes are scrolled and prioritized normally, but bypass color table and 8 bit wide data appear on R(7:0). RST_pin resets all bits in all registers new to AA. These registers include: BPLCON3, BPLCON4, CLXCON2, DIWHIGH, FMODE. ECSENA bit (formerly ENBPLCN3) is used to disable those register bits in BPLCON3 that are never accessed by old copper lists, and in addition are required by old-style copper lists to be in their default settings. Specifically, ECSENA forces the following bits to their default low settings: BRDRBLNK, BRDNTRAN, ZDCLKEN, EXTBLKEN, and BRDRSPRT. When ECSENA is set high again, the former settings for these bits are restored. CLXCON2 is reset by a write to CLXCON, so that old game programs will be able to correctly detect collisions. * bplcon1 EQU $102 ; bits 8 to 14 used for 1/4 pixel scroll ; 2 bits are for displacing the pixels in ; steps of 1/4 for the odd planes and 2 for ; the even planes. the other 2 pairs of bits ; are for scrolling in steps of 16 pixels a ; time (one pair for odd planes and one pair ; for even). This means that you can move any ; playfield 64 pixels to any side with ; intervals of 1/4 pixel!!! ; you have 256 possible scrollvalues=8bits... 15 PF2H7 - 64 PIXEL SCROLL PF2 (AGA) 14 PF2H6 - 64 PIXEL SCROLL PF2 (AGA) 13 PF2H1 - FINE SCROLL PF2 (AGA SCROLL 35ns 1/4 of pixel) 12 PF2H0 - FINE SCROLL PF2 11 PF1H7 - 64 PIXEL SCROLL PF1 (AGA) 10 PF1H6 - 64 PIXEL SCROLL PF1 (AGA) 09 PF1H1 - FINE SCROLL PF1 (AGA SCROLL 35ns 1/4 of pixel) 08 PF1H0 - FINE SCROLL PF1 07 PF2H3 06 PF2H2 05 PF2H1 04 PF2H0 03 PF1H3 02 PF1H2 01 PF1H1 00 PF1H0 PF2H=Playfield 2 scroll code PFlH=Playfield 1 scroll code PF2Hx = Playfield 2 horizontal scroll code, x=0-7 PF1Hx = Playfield 1 horizontal scroll code, x=0-7 where PFyH0=LSB=35ns SHRES pixel (bits have been renamed, old PFyH0 now PFyH2, ect). Now that the scroll range has been quadrupled to allow for wider (32 or 64 bits) bitplanes. - Smooth Hardware Scrolling (from howtocode 6) Extra bits have been added to BPLCON1 to allow smoother hardware scrolling and scrolling over a larger area. Bits 8 (PF1H0) and 9 (PF1H1) are the new hi-resolution scroll bits for playfield 0 and bits 12 (PF2H0) and 13 (PF2H1) are the new bits for playfield 1. Another two bits have been added for each bitplane at bits 10 (PF1H6) and 11 (PF1H7) for playfield 1 and bits 14 (PF2H6) and 15 (PF2H7) to increase the maximum scroll range from 16 lo-res pixels to 64 lo-res pixels (or 256 superhires pixels). Normal 0-16 positions therefore are normal, but it you want to position your screen at a (super) hires position you need to set the new bits, or if you require smooth hardware scrolling with either 2x or 4x Fetch Mode. * bplcon2 EQU $104 ; Bit Plane Control Register 2 (video priority control) 15 - 14 ECS ZDBPSEL2 \ Select one of the 8 BitPlanes 13 ECS ZDBPSEL1 } in ZDBPEN genlock mod 12 ECS ZDBPSEL0 / 11 ECS ZDBPEN Use BITPLANEKEY - use bitplane as genlock bits 10 ECS ZDCTEN Use COLORKEY - colormapped genlock bit 09 ECS KILLEHB Kill ExtraHalfBrite (for a normal 6bpl pic) 08 AGA RDRAM All color tabs are reads 07 AGA SOGEN (ZDCLKEN) Enable 14Mhz clock 06 PF2PRI PField 2 priority over PField 1 05 PF2P2 \ 04 PF2P1 } PField 2 sprite priority 03 PF2P0 / 02 PF1P2 \ 01 PF1P1 } PField 1 sprite priority 00 PF1P0 / Using 64-colour mode (NOT extra halfbrite) requires setting the KILLEHB (bit 9) in BPLCON2. ZDBPSELx =3 bit field which selects which bitplane is to be used for ZD when ZDBBPEN is set;000 selects BB1 and 111 selects BP8. ZDBPEN = Causes ZD pin to mirror bitplane selected by ZDBPSELx bits. This does not disable the ZD mode defined by ZDCTEN, but rather is "ored" with it. ZDCTEN = Causes ZD pin to mirror bit #15 of the active entry in high color table. When ZDCTEN is reset ZD reverts to mirroring color (0). SOGEN = When set causes SOG output pin to go high RDRAM bit in BPLCON2 causes LISA to interpret all colour table accesses as reads instead of writing to it. Lots of new genlock features were added to ECS denise and are carried over to LISA. ZDBPEN in BPLCON2 allows any bitplane, delected by ZDBPSEL2,1,0, to be used as a tansparency mask (ZD pin mirrors contents of selected bitplane). ZDCTEN disables the old COLOUR00 is transparent mode, and allows the bit-31 position of each colour in the colour table to control transparency . ZDCLKEN generates a 14MHz clock synchronized with the video data that can be used by video post-processors. * bplcon3 EQU $106 ; 0 = EXTBLNKEN - external blank enable ; 1 = BRDSPRT - EXTBLKZD - external blank ored ; into trnsprncy- sprites on BORDERS! ; 2 = ZDCLKEN - zd pin outputs a 14mhz cloc ; 3 = NO FUNCTIONS - SET TO ZERO ; 4 = ECS BRDRTRAN Border opaque ; 5 = ECS BRDRBLNK Border blank ; 6 = AGA SPRES1 \sprite hires,lores,superhires ; 7 = AGA SPRES0 / ; 8 = NO FUNCTIONS - SET TO ZERO ; 9 = LOCT - palette high or low nibble colour ; 10 = PF2OF2 \ ; 11 = PF2OF1 } second playfield's offset in coltab ; 12 = PF2OF0 / ; 13 = BANK0 \ ; 14 = BANK1 } LOCT palette select 256 ; 15 = BANK2 / ; BANKx = Selects one of eight color banks, x=0-2. Bits PF2OF2,1,0 in BPLCON3 determine second playfield's offset into the colour table. This is now necessary since playfields in DPF mode can have up to 4 bitplanes. Offset values are as defined in register map. The bits 10 and 11 must be set as default to made the old 16 colours dual playfiled, so remember that ($106,$c00) (Thanx to MUCSI/Muffbusters) PF20Fx = Determine bit plane color table offset whe playfield 2 has priority in dual playfield mode: PF20F || AFFECTED BITPLANE ||OFFSET (From C-18 AGA doc) ------------------------------------------------------- | 2 | 1 | 0 || 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 ||(decimal) ------------------------------------------------------- | 0 | 0 | 0 || - | - | - | - | - | - | - | - || none | 0 | 0 | 1 || - | - | - | - | - | - | 1 | - || 2 | 0 | 1 | 0 || - | - | - | - | - | 1 | - | - || 4 | 0 | 1 | 1 || - | - | - | - | - | 1 | - | - || 8 (default) | 1 | 0 | 0 || - | - | - | 1 | - | - | - | - || 16 | 1 | 0 | 1 || - | - | 1 | - | - | - | - | - || 32 | 1 | 1 | 0 || - | 1 | - | - | - | - | - | - || 64 | 1 | 1 | 1 || 1 | - | - | - | - | - | - | - || 128 LOCT = Dictates that subsequent color palette values will be written to a second 12- bit color palette, constituting the RGB low minus order bits. Writes to the normal hi monus order color palette automattically copied to the low order for backwards compatibility. (selects either the 16 MSB or LSB for loading) BRDNTRAN in BPLCON3 generates an opaque border region which can be used to frame live video. (Genlock) BRDRBLNK = "Border area" is blanked instead of color (0). Disabled when ECSENA low. BRDRSPRT, when high, allows sprites to be visible out the display window. but if you want it to work you have to enable ECSENA. This is bit 0 from $dff100! (this is for compatibilty reasons!) ZDCLKEN = ZD pin outputs a 14MHz clock whose falling edge coincides with hires (7MHz) video data. this bit when set disables all other ZD functions. Disabled when ESCENA low. EXTBLKEN = causes BLANK output to be programmable instead of reflecting internal fixed decodes. Disabled when ESCENA low. * bplcon4 EQU $10C ; 0 ESPRM7 \ ; 1 ESPRM6 \ CHOOSE EVEN SPRITE PALETTE ; 2 ESPRM5 / ; 3 ESPRM4 / ; 4 OSPRM4 \ ; 5 OSPRM4 \ CHOOSE ODD SPRITE PALETTE ; 6 OSPRM4 / ; 7 OSPRM4 / ; 8 BPLAM0 \ ; 9 BPLAM1 \ ; 10 BPLAM2 | ; 11 BPLAM3 | Switch colours without ; 12 BPLAM4 | change the palette ; 13 BPLAM5 | ; 14 BPLAM6 / ; 15 BPLAM7 / BPLAMx = This 8 bit field is XOR`ed with the 8 bit plane color address,thereby altering the color address sent to the color table (x=1-8) Bits 15 thru 8 of BPLCON4 comprise an 8-bit mask for the 8 bitplane address, XOR'ing the individual bits. This allows the copper to exchange colour maps with a single instruction. ESPRMx = 4 Bit field provides the 4 high order color table address bits for even sprites: SPR0,SPR2,SPR4,SPR6. Default value is 0001 binary. (x=7-4) OSPRMx = 4 Bit field provides the 4 high order color table address bits for odd sprites: SPR1,SPR3,SPR5,SPR7. Default value is 0001 binary. (x=7-4) * clxcon2 EQU $10E ; 0 match value for bitplane 7 collision ; 1 match value for bitplane 8 collision ; 2-5: UNUSED ; 6 ENBP8 enable bitplane 7 (match reqd coll) ; 7 ENBP8 enable bitplane 8 (match reqd coll) ; 8-15: UNUSED A new register CLXCON2 contains 4 new bits. ENBP7 and ENBP6 are the enable bits for bitplanes 7 and 8, respectively. Similarly, MVBP7 and MVBP8 are their match value bits. CLXDAT is unchanged. * BPL7DAT EQU $11c W ;Bit plane 7 data (parallel to serial convert) BPL8DAT EQU $11e W ;Bit plane 8 data (parallel to serial convert) * SPRxPOS EQU $140/... ;Sprite x vert-horiz start position data. BIT# SYM FUNCTION ---- ---- ----------------------------------------- 15-08 SV7-SV0 Start vertical value.High bit (SV8) is in SPRxCTL register below. 07-00 SH10-SH3 Sprite horizontal start value. Low order 3 bits are in SPRxCTL register below. If SSCAN2 bit in FMODE is set, then disable SH10 horizontal coincidence detect.This bit is then free to be used by ALICE as an individual scan double enable. * sprxctl EQU $142/14A/152/15A/162/16A/172/17A Sprite x vert stop and control data BIT# SYM FUNCTION ---- ---- ---------------------------------------- 15-08 EV7-EV0 End (stop) vert. value. Low 8 bits 07 ATT Sprite attach control bit (odd sprites only) 06 AGA SV9 Start vert value 10th bit. 05 AGA EV9 End (stop) vert. value 10th bit 04 ECS SH1=0 Start horiz. value, 70nS increment 03 AGA SH0=0 Start horiz. value 35nS increment 02 SV8 Start vert. value 9th bit 01 EV8 End (stop) vert. value 9th bit 00 SH2 Start horiz.value,140nS increment These 2 registers work together as position, size and feature sprite control registers.They are usually loaded by the sprite DMA channel, during horizontal blank, however they may be loaded by either processor any time. Writing to SPRxCTL disables the corresponding sprite. * 144/146/14C/14E/154/156/15C/15E/164/166/16C/16E/174/176/17C/17E Sprite image Data (From C-18 AGA doc) These registers buffer the sprite image data.They are usually loaded by the sprite DMA channel but may be loaded by either processor at any time. When a horizontal coincidence occurs the buffers are dumped into shift registers and serially outputed to the display, MSB first on the left. NOTE: Writing to the A buffer enables (arms) the sprite. Writing to the SPRxCTL registers disables the sprite. If enabled, data in the A and B buffers will be output whenever the beam counter equals the sprite horizontal position value in the SPRxPOS register. In lowres mode, 1 sprite pixel is 1 bitplane pixel wide.In HRES and SHRES mode, 1 sprite pixel is 2 bitplane pixels. The DATB bits are the 2SBs (worth 2) for the color registers, and MSB for SHRES. DATA bits are LSBs of the pixels. * COLORxx 180-1BE W COLOR table xx (From C-18 AGA DOC) There 32 of these registers (xx=00-31) and together with the banking bits they address the 256 locations in the color palette. There are actually two sets of color regs, selection of which is controlled by the LOCT reg bit. When LOCT = 0 the 4 MSB of red, green and blue video data are selected along with the T bit for genlocks the low order set of registers is also selected as well, so that the 4 bi valuesare automatically extended to 8 bits. This provides compatibility with old software. If the full range of palette values are desired, then LOCT can be set high and independant values for the 4 LSB of red, green and blue can be written. The low order color registers do not contain a transparency (T) bit. The table below shows the color register bit usage. BIT# 15,14,13,12 11,10,09,08 07,06,05,04 03,02,01,00 ---- ----------- ----------- ----------- ----------- LOCT=0 T X X X R7 R6 R5 R4 G7 G6 G5 G4 B7 B6 B5 B4 LOCT=1 X X X X R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 T = TRANSPARENCY R = RED G = GREEN B = BLUE X = UNUSED T bit of COLOR00 thru COLOR31 sets ZD_pin HI, When that color is selected in all video modes. * htotal EQU $1c0 ; Highest number count, horiz line ; (VARBEAMEN bit in BEAMCON0 must be set) HTOTAL W A Highest number count in horizontal line Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 10 00 Use 0 0 0 0 0 0 0 0 h8 h7 h6 h5 h4 h3 h2 h1 Horiz line has theis many + 1 280nS increments. If the pal bit & LOLDIS are not high, long line/skort line toggle will occur, and there will be this many +2 every other line. Active if VARBEAMEN=1 or DUAL+1. * hsstop EQU $1c2 ; Horizontal line position for HSYNC stop Sets # of colour clocks for sync stop (HTOTAL for bits) * hbstrt EQU $1c4 ; Horizontal line position for HBLANK start hbstop EQU $1c6 ; Horizontal line position for HBLANK stop Bits 7-0 contain the stop and start positions, respectively, for programed horizontal blanking in 280nS increments.Bits 10-8 provide a fine position control in 35nS increments. BIT# FUNCTION DESCRIPTION (from C-18 AGA doc) ---- -------- ----------- 15-11 x (unused) 10 H1 140nS 09 H1 70nS 08 H0 35nS 07 H10 35840nS 06 H9 17920nS 05 H8 8960nS 04 H7 4480nS 03 H6 2240nS 02 H5 1120nS 01 H4 560nS 00 H3 280nS * vtotal EQU $1c8 ; Highest numbered vertical line ; (VARBEAMEN bit in BEAMCON0 must be set) VTOTAL W A Highest numbered vertical line VTOTAL contains the line number at which to reset the vertical position counter. This value represents the number of lines in a field(+1). The exception is if the INTERLACE bit is set (BPLCON0). In this case this value represents the number of lines in the long field (+2) and the number of lines in the short field (+1). * vsstop EQU $1ca ; Vertical line position for VSYNC stop * vbstrt EQU $1cc ; Vertical line for VBLANK start vbstop EQU $1ce ; Vertical line for VBLANK stop (V10-0 <- D10-0) Affects CSY pin if BLAKEN=1 and VSY pin if CSCBEN=1 (BEAMCON0) * sprhstrt EQU $1d0 ;UHRES sprite vertical displat start BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 x x x x x v10 v9 v8 v7 v6 v5 v4 v3 v2 v1 v0 * sprhstop EQU $1d2 ;UHRES sprite vertical display stop BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SPRHWRM x x x x x v10 v9 v8 v7 v6 v5 v4 v3 v2 v1 v0 SPRHWRM = Swaps the polarity of ARW* when the SPRHDAT comes out so that external devices can detect the RGA and put things into memory.(ECS and later chips only) * bplhstrt EQU $1d4 ;UHRES bit plane vertical start This controls the line when the data fetch starts for the BPLHPTH,L pointers. V10-V0 on DB10-0. * bplhstop EQU $1d6 ;UHRES bit plane vertical stop BIT# name ---- ---- 15 BPLHWRM 14-11 Unused 10-0 V10-V0 BPLHWRM = Swaps the polarity of ARW* when the BPLHDAT comes out so that external devices can detect the RGA and put things into memory (from ECS) * hhposw EQU $1d8 ;DUAL mode hires H beam counter write hhposr EQU $1da ;DUAL mode hires H beam counter read This the secondary beam counter for the faster mode, triggering the UHRES pointers & doing the comparisons for HBSTRT,STOP,HTOTAL,HSSRT,HSSTOP (See HTOTAL for bits) * beamcon0 EQU $1dc ; Beam counter control register (ECS) ; (SHRES,UHRES,PAL) 15 - 14 ECS HARDDIS Disable Hardwired vert/hor blank 13 ECS LPENDIS Ignore latched pen value on vert pos read 12 ECS VARVBEN Variable vertical blank enable Use VBSTRT/STOP disable hard window stop 11 ECS LOLDIS Disable longline/shortline toggle 10 ECS CSCBEN Composite sync redirection 09 ECS VARVSYEN Variable vertical sync enable 08 ECS VARHSYEN Variable horizontal sync enable 07 ECS VARBEAMEN Variable beam counter comparator enable 06 ECS DISPLAYDUAL Special ultra resolution enable (use UHRES pointer and standard pointers) 05 ECS DISPLAYPAL Programmable PAL mode enable (pal/ntsc switch) 04 ECS VARCSYEN Variable composite sync enable 03 ECS BLANKEN-CSBLANK Composite blank redirection (out to CSY pin) 02 ECS CSYNCTRUE Polarity control for Composite sync pin (TRUE) 01 ECS VSYNCTRUE Polarity control for Vertical sync pin (TRUE) 00 ECS HSYNCTRUE Polarity control for Horiz sync pin (TRUE) (From C-18 AGA DOC) HARDDIS = This bit is used to disable the hardwire vertical horizontal window limits. It is cleared upon reset. LPENDIS = When this bit is a low and LPE (BPLCON0,BIT 3) is enabled, the light-pen latched value(beam hit position) will be read by VHPOSR,VPOSR and HHPOSR. When the bit is a high the light-pen latched value is ignored and the actual beam counter position is read by VHPOSR,VPOSR, and HHPOSR. VARVBEN = Use the comparator generated vertical blank (from VBSTRT,VBSTOP) to run the internal chip stuff-sending RGA signals to Denise, starting sprites,resetting light pen. It also disables the hard stop on the vertical display window. LOLDIS = Disable long line/short toggle. This is useful for DUAL mode where even multiples are wanted, or in any single display where this toggling is not desired. CSCBEN = The variable composite sync comes out on the HSY pin, and the variable conosite blank comes out on the VSY pin. The idea is to allow all the information to come out of the chip for a DUAL mode display. The normal monitor uses the normal composite sync, and the variable composite sync &blank come out the HSY & VSY pins. The bits VARVSTEN & VARHSYEN (below) have priority over this control bit. VARVSYEN= Comparator VSY -> VSY pin. The variable VSY is set vertically on VSSTRT, reset vertically on VSSTOP, with the horizontal position for set set & reset HSSTRT on short fields (all fields are short if LACE = 0) and HCENTER on long fields (every other field if LACE = 1). VARHSYEN= Comparator HSY -> HSY pin. Set on HSSTRT value, reset on HSSTOP value. VARBEAMEN=Enables the variable beam counter comparators to operate (allowing diffrent beam counter total values) on the main horiz counter. It also disables hard display stops on both horizontal and vertical. DUAL = Run the horizontal comparators with the alternate horizontal beam counter, and starts the UHRES pointer chain with the reset of this counter rather than the normal one. This allows the UHRES pointers to come out more than once in a horizontal line, assuming there is some memory bandwidth left (it doesn`t work in 640*400*4 interlace mode) also, to keep the two displays synced, the horizontal line lentghs should be multiples of each other. If you are amazingly clever, you might not need to do this. PAL = Set appropriate decodes (in normal mode) for PAL. In variable beam counter mode this bit disables the long line/short line toggle- ends up short line. VARCSYEN= Enables CSY from the variable decoders to come out the CSY (VARCSY is set on HSSTRT match always, and also on HCENTER match when in vertical sync. It is reset on HSSTOP match when VSY and on both HBSTRT &HBSTOP matches during VSY. A reasonable composite can be generated by setting HCENTER half a horiz line from HSSTRT, and HBSTOP at (HSSTOP-HSSTRT) before HCENTER, with HBSTRT at (HSSTOP-HSSTRT) before .... see below * HSSTRT EQU $1DE ; Horizontal sync start (VARHSY) Sets # of colour clocks for sync start (HTOTAL for bits) See BEAMCON0 for details of when these 2 are active. * vsstrt EQU $1e0 ; Vertical sync start (VARVSY) ; (VARVSYEN bit in BEAMCON0 must be set) * hcenter EQU $1e2 ; Horizontal position for VSynch on interlace ; (or CCKs on long field) this is necessary for interlace mode with variable beam counters. See BEAMCON0 for when it affects chip outputs. See HTOTAL for bits. * diwhigh EQU $1e4 ; highest bits for the diwstrt/stop DIWHIGH is reset by writes to DIWSTRT or DIWSTOP. This interlock is inherited from ECS Denise. Display window upper bits for start, stop this is an added register for Hires chips, and allows larger start & stop ranges. If it is not written, the above (DIWSTRT,STOP) description holds. If this register is written, direct start & stop positions anywhere on the screen. It doesn`t affect the UHRES pointers. BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 X X H10 H1 H0 V10 V9 V8 X X H10 H1 H0 V10 V9 V8 (stop) | (start) Take care (X) bits should always be written to 0 to maintain upwards compatibility. H1 and H0 values define 70ns amd 35ns increments respectively, and new LISA bits. NOTE: In all 3 display window registers, horizontal bit positions have been renamed to reflect HIRES pixel increments, e.g. what used to be called H0 is now referred to as H2. * BPLHMOD EQU $1E6 ; modulo of the bitplane of UHRES ;This is the number (sign extended) that is added to the ;UHRES bit plane pointer (BPLHPTL,H) every line, and ;then another 2 is added, just like the other modulos. * SPRHPTH EQU $1E8 ; sprite pointer for UHRES (high 5 bits) SPRHPTL EQU $1EA ; sprite pointer for UHRES (low 15 bits) This pointer is activated in the 1st and 3rd `free` cycles (see BPLHPTH,L) after horiz line start.It increments for the next line. * BPL1HPTH EQU $1EC ; VRAM BITPLANE POINTER FOR UHRES (high 5 bits) * BPL1HPTL EQU $1EE ; VRAM BITPLANE POINTER FOR UHRES (low 15 bits) When UHRES is enabled, this pointer comes out on the 2nd 'free' cycle after the start of each horizontal line. It`s modulo is added every time it comes out. 'free' means priority above the copper and below the fixed stuff (audio,sprites....). BPLHDAT comes out as an identifier on the RGA lines when the pointer address is valid so that external detectors can use this to do the special cycle for the VRAMs, The SHRHDAT gets the first and third free cycles. * fmode EQU $1fc ; 0 = BPL32 - bitplane 32 bit wide mode ; 1 = BPAGEM - bitplane page mode (double cas) (REMEMBER to align 32 or 64 bits the bitplanes) ; 2 = SPR32 -sprite 32 bit wide mode ; 3 = SPAGEM -sprite page mode (double cas) (REMEMBER to align 32 or 64 bits the sprite) ; 4-13 = UNUSED ; 14 = BSCAN2 enabled use of 2nd P/F modulus on an ; alternate line basis to suppott bitplane scan doubling! (probably for fancy monitors!) ; 15 = SSCAN2, global enable for sprite scan doubling BPAGEM BPL32 Bitplane Fetch Increment Memory Cycle Bus Width ------------------------------------------------------------ 0 0 By 2 bytes (as before) normal CAS 16 0 1 By 4 bytes normal CAS 32 1 0 By 4 bytes double CAS 16 1 1 By 8 bytes double CAS 32 SPAGEM SPR32 Sprite Fetch Increment Memory Cycle Bus Width ------------------------------------------------------------ 0 0 By 2 bytes (as before) normal CAS 16 0 1 By 4 bytes normal CAS 32 1 0 By 4 bytes double CAS 16 1 1 By 8 bytes double CAS 32 SSCAN2 bit in FMODE enables sprite scan-doubling. When enabled, individual SH10 bits in SPRxPOS registers control whether or not a given sprite is to be scan-doubled. When V0 bit of SPRxPOS register matches V0 bit of vertical beam counter, the given sprite's DMA is disabled and LISA reuses the sprite data from the previous line. When sprites are scan-doubled, only the position and control registers need be modified by the programmer; the data registers need no modification. NOTE: Sprite vertical start and stop positions must be of the same parity, i.e. both odd or both even. For non-interlaced screens, bitplane scandoubling is enabled (bit 14 BSCAN2 in FMODE) This repeats each scanline twice. A side effect of this is that the bitplane modulos are unavailable for user control. BSCAN bit 14 in FMODE enables bitplane scan-doubling. When V0 bit of DIWSTRT matches V0 of vertical beam counter, BPL1MOD contains the modulus for the display line, else BPLMOD is used. When scan-doubled both odd and even bitplanes use the same modulus on a given line, whereas in normal mode odd bitplanes used BPL1MOD and even bitplanes used BPL2MOD. As a result Dual Playfield screens will probably not display correctly when scan-doubled. DDFSTRT and DDFSTOP values should be modified if you change the burst mode. (From YRAGAEL & JUNKIE doc) Eg: If you use LONG burst mode to open an Hires screen starting at hardware horizontal position STARTX: DDFSTRT=(STARTX-17)/2 and no more DDFSTRT=(STARTX-9)/2 Why ? Very easy. You need 4 cycles to read a word (using all the bitplanes) in Hires. If you want the image to start at STARTX, you must read the first word 4 cycles before its horizontal position. Add 0.5 cycles (it's needed !). This gives DDFSTRT=(STARTX-9)/2. If you are in LONG burst mode, then you will read a long. This will take 8 cycles. So you must read the first long 8.5 cycles before the STARTX position: DDFSTRT=(STARTX-17)/2. That's all. - The Magic FMode Register (from howtocode6.txt) If you set your 1200/4000 to a hiresmode (such as 1280x512 Superhires 256 colours) and disassemble the copperlist, you find fun things happen to the FMODE register ($dff1fc). The FMODE register determines the amount of words transferred between chipram and the Lisa chip in each data fetch. NOTE: Using a data fetch > 0 in standard LOWRES or in hires resolutions, the COPPERLIST will be faster (will leave free more time for the 680x0 and blitter), but the BLITTER speed is the SAME. $dff1fc bits 0 and 1 value $00 - Normal (word aligned bitmaps) - for standard ECS modes and up to 8 bitplanes 320x256 $01 - Double (longword aligned bitmaps) - for 640x256 modes in more than 16 colours $10 - Double (longword aligned bitmaps) - Same effect, for 640x256 modes but different things happen... Not sure why! $11 - Quadruple [x4] (64-bit aligned bitmaps) - for 1280x256 modes... - Fetch Mode Required for Displays *ALL* ECS and lower screenmodes require only 1x datafetch. All modes run *FASTER* with at least 2x bandwidth, so try and use 2x bandwitdh if possible. Bits 2 and 3 do the same for sprite width, as has been mentioned elsewhere... Remember... To take advantage of the increased fetchmodes (which give you more processor time to play with!) your bitmaps must be on 64-bit boundaries and be multiples of 64-bits wide (8 bytes) * New for AA ChipSet (V39) - $DFF100 - HIRES HAM : %1000100000000000 - LACE: %1000100000000100 SUPERHIRES HAM : %1000100001000000 - LACE: %1000100001000100 (is possible to do hires and superhires EHB) * Bitplanes: Set 0 to 7 bitplanes as before in $dff100. Set 8 bitplanes by setting bit 4 of $dff100, bits 12 to 15 should be zero. For Hires when you have 8 bitplanes remember to set the bit 0 and 1 of $dff1fc 8 bitplanes: The number of bitplanes used to be specify with bits 14 to 12 of register $DFF0100. Since there were just 3 bits, it would have been impossible to use more than 7 bitplanes. To use 8 bitplanes, switch bit 4 of register $DFF100. Don't forget to clear bits 14 to 12 for further compatiblity :). bit 4 | 8 bitplanes mode ------------------------ 0 | Not Selected ------------------------ 1 | Selected ------------------------ Using 64-colour mode (NOT extra halfbrite) requires setting the KILLEHB (bit 9) in BPLCON2. * Colour Registers: There are now 256 colour registers, all accessed through the original 32 registers AGA works with 8 differents palettes of 32 colors each, re-using colour registers from $0180 to $01BE. You can choose the palette you want to access via the bits 13 to 15 of register $0106 bit 15 | bit 14 | bit 13 | Selected palette -------+--------+--------+------------------------------ 0 | 0 | 0 | Palette 0 (color 0 to 31) 0 | 0 | 1 | Palette 1 (color 32 to 63) 0 | 1 | 0 | Palette 2 (color 64 to 95) 0 | 1 | 1 | Palette 3 (color 96 to 127) 1 | 0 | 0 | Palette 4 (color 128 to 159) 1 | 0 | 1 | Palette 5 (color 160 to 191) 1 | 1 | 0 | Palette 6 (color 192 to 223) 1 | 1 | 1 | Palette 7 (color 224 to 255) * To move a 24-bit colour value into a colour register requires two writes to the register: First clear bit 9 of $dff106 Move high nibbles of each colour component to colour registers Then set bit 9 of $dff106 Move low nibbles of each colour components to colour registers bit 9 | Access ------------------------------------------------ 0 | Access to 4 high bits of R,G,B components ------------------------------------------------ 1 | Access to 4 low bits of R,G,B components ------------------------------------------------ You must respect the order: first move the 3*4 HIGH bits and then the 3*4 LOW bits !